Galois field computation LSI: a reconfigurable chip for high-speed communication

A new reconfigurable LSI for Galois field computation has been developed, implementing high-speed operation while maintaining general FPGA versatility. Customized for high-speed communication applications, the chip bridges the performance gap between custom LSIs and FPGAs. Including two types of building blocks optimally designed for Galois field computation, performance of the chip is 2 to 10 times faster than for FPGAs, providing parallel data transmission for on-board and back-plane connections (2Gbps on each 70cm-line).

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