A low power hardware implementation of S-Box for Advanced Encryption Standard

This paper presents a low power custom hardware implementation of Rijndael S-Box for Advanced Encryption Standard (AES). This custom hardware was designed by using combinational logic unlike the previous works which rely on look-up tables and memory to implement the S-Box. The minimization of power consumption is implemented by optimizing the architecture of the composite field S-Box together with using of pass transmission gate (PTG) to realize the logic functions. The circuits were designed using the DSCH3 VLSI CAD tool and the layouts were drawn by using the Microwind 3 VLSI CAD tool. The post layout netlist was then evaluated in terms of power dissipation, propagation delay, power and area by performing detailed transistor-level simulations by using LTSpice ver4.13 CAD simulator. The simulated results of these circuits were compared with other published results, where better performance was observed for power dissipation with as low as 106.2μW at 10MHz and lower propagation delay of 5ps. The simulations also showed that the presented S-Box has 20.1% reduction in power consumption as compared to the recent published paper.

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