Complete SAT Solver Based on Set Theory

SAT problem is a NP-complete. Many SAT benchmarks that come from the different real life SAT problems are proposed to verify the performance of solvers. Our research focuses on the Model RB benchmark which can be mapped by the coloring problem and others. We propose a translating method based on set for Model RB instances of CNF formulas, and a complete search algorithm. We use the weight of clauses based on the set to determine the order of the search. The results show our solver has the best runtime for the mostly instances and is comparable to the best SAT solvers.

[1]  Per Bjesse,et al.  Finding Bugs in an Alpha Microprocessor Using Satisfiability Solvers , 2001, CAV.

[2]  Stephanie Kemper SAT-based Verification for Timed Component Connectors , 2009, Electron. Notes Theor. Comput. Sci..

[3]  Hilary Putnam,et al.  A Computing Procedure for Quantification Theory , 1960, JACM.

[4]  Wei Li,et al.  Exact Phase Transitions in Random Constraint Satisfaction Problems , 2000, J. Artif. Intell. Res..

[5]  Gilles Audemard,et al.  A Restriction of Extended Resolution for Clause Learning SAT Solvers , 2010, AAAI.

[6]  Xiaoyu Song,et al.  Defect-Tolerant CMOL Cell Assignment via Satisfiability , 2008, IEEE Sensors Journal.

[7]  Guowu Yang,et al.  Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Guowu Yang,et al.  Routability checking for three-dimensional architectures , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[9]  Min Zhou,et al.  An Efficient Resolution Based Algorithm for SAT , 2011, 2011 Fifth International Conference on Theoretical Aspects of Software Engineering.

[10]  Krzysztof Czarnecki,et al.  SAT-based analysis of feature models is easy , 2009, SPLC.

[11]  Andrew A. Kennings,et al.  Board-level multiterminal net assignment for the partial cross-bar architecture , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[12]  Xiaoyu Song,et al.  Segmented channel routability via satisfiability , 2004, TODE.

[13]  John Franco,et al.  Probabilistic analysis of the Davis Putnam procedure for solving the satisfiability problem , 1983, Discret. Appl. Math..

[14]  Donald W. Loveland,et al.  A machine program for theorem-proving , 2011, CACM.

[15]  Rob A. Rutenbar,et al.  FPGA routing and routability estimation via Boolean satisfiability , 1997, FPGA '97.

[16]  Fabio Somenzi,et al.  Making Deduction More Effective in SAT Solvers , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[17]  William N. N. Hung,et al.  Reference model based RTL verification: an integrated approach , 2004, Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940).

[18]  Masahiro Fujita,et al.  Symbolic model checking using SAT procedures instead of BDDs , 1999, DAC '99.

[19]  Ming Gu,et al.  A satisfiability formulation for FPGA routing with pin rearrangements , 2007 .

[20]  Tracy Larrabee,et al.  Test pattern generation using Boolean satisfiability , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..