Low energy, low latency and high speed array divider circuit using a shannon theorem based adder cell.

The paper discuss the design of 1-bit full adder circuit using Shannon theorem. This proposed full adder circuit is used as one of the circuit component for implementation of Non- Restoring and Restoring divider circuits. The proposed adder and divider schematics are designed by using DSCH2 CAD tool and their layouts are generated by Microwind 3 VLSI CAD tool. The divider circuits are designed by using standard CMOS 0.35 microm feature size and corresponding power supply 3.5 V. The parameters analyses are carried out by BSIM 4 analysis. We have compared the simulated results of the Shannon based divider circuit with CPL and CMOS adder cell based divider circuits. We have further compared the results with published results and observed that the proposed adder cell based divider circuit dissipates lower power, gives faster response, lower latency, low EPI and high throughput.

[1]  C. Senthilpari,et al.  Low power and high speed 8x8 bit multiplier using non-clocked pass transistor logic , 2007, 2007 International Conference on Intelligent and Advanced Systems.

[2]  Massimo Alioto,et al.  Analysis and comparison on full adder block in submicron technology , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[3]  E.E. Swartzlander,et al.  Design of Radix 4 SRT Dividers for Single Precision DSP in Deep Submicron CMOS Technology , 2006, 2006 IEEE International Symposium on Signal Processing and Information Technology.

[4]  H. Magnusson,et al.  A 1.8-V wide-band CMOS LNA for multiband multistandard front-end receiver , 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).

[5]  Shen-Fu Hsiao,et al.  High-performance multiplexer-based logic synthesis using pass-transistor logic , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[6]  C. Senthilpari,et al.  Statistical analysis of Power Delay Estimation in adder circuit using non-clocked pass gate families , 2006, 2006 International Conference on Electrical and Computer Engineering.

[7]  Wayne Luk,et al.  Hardware Generation of Arbitrary Random Number Distributions From Uniform Distributions Via the Inversion Method , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Donald A. Neamen,et al.  Microelectronics Circuit Analysis and Design , 2006 .

[9]  Chip-Hong Chang,et al.  A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits , 2005 .

[10]  Alexander Chatzigeorgiou,et al.  Output Waveform Evaluation of Basic Pass Transistor Structure , 2002, PATMOS.

[11]  Viktor Öwall,et al.  A configurable divider using digit recurrence , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[12]  Behrooz Parhami,et al.  Computer arithmetic - algorithms and hardware designs , 1999 .

[13]  Alexander Chatzigeorgiou,et al.  Efficient output waveform evaluation of a CMOS inverter based on short‐circuit current prediction , 2002, Int. J. Circuit Theory Appl..

[14]  Mohamed I. Elmasry.  Digital VLSI systems , 1985 .

[15]  John Crawford,et al.  Performance Characterization of Decimal Arithmetic in Commercial Java Workloads , 2007, 2007 IEEE International Symposium on Performance Analysis of Systems & Software.

[16]  C. Senthilpari,et al.  Power Deduction in Digital Signal Processing Circuit using Inventive CPL Subtractor Circuit , 2006, 2006 IEEE International Conference on Semiconductor Electronics.

[17]  Michael J. Flynn,et al.  Division Algorithms and Implementations , 1997, IEEE Trans. Computers.

[18]  Vojin G. Oklobdzija,et al.  General method in synthesis of pass-transistor circuits , 2000 .