Evaluating and mitigating degradation effects in multimedia circuits

The nano-CMOS era continuously introduces reliability challenges with every new generation. Short-term and long-term degradation effects due to temperature and aging, respectively, can cause a considerable increase in the delay of a circuit and hence timing errors due to path violations. To overcome such degradations, designers inevitably need to employ wide timing guardbands manifest as reduced efficiency and performance. In fact, narrowing guardbands is one of the key optimization goals in current and upcoming technology nodes. In this work, we investigate whether do designers really need to employ guardbands even in error-tolerant (e.g., multimedia) circuits? This investigation enables us to trade off guardbands with quality. In addition, we demonstrate how our proposed degradation-aware cell libraries, degradation-aware timing analysis and degradation-aware logic synthesis are indispensable, not only to link the physical level with the system level (i.e. quantifying the final impact of degradation effects on the quality of processed images) but also to increase effectively the resiliency of circuits against degradations.