论文信息 - FPGA implementation of the dynamic Huffman Encoder

FPGA implementation of the dynamic Huffman Encoder

Abstract At first part of this paper, the architecture for quasi-static Huffman encoder is described which main part is Look-Up Table (LUT). In order to reduce the hardware requirements, the maximum length of the encoded word is limited. This reduces the compression ratio insignificantly which is proved in this paper. The dynamic encoding is achieved by a change of the LUT contents and hardware-software co-design approach. Consequently counting the input words statistics (histogram) and sorting the resultant histogram is implemented in hardware. The final calculation of the new LUT contents and controlling the whole system is achieved by the soft-processor Micro Blaze.

Maciej Wielgosz | Ernest Jamro | Kazimierz Wiatr

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