Sensitivity analysis of testability parameters for secure IC design

Insertion of malicious circuits commonly known as Hardware Trojans into an original integrated circuit (IC) design to alter the functionality has been a major concern in recent years. As a result, over the years multiple techniques have been suggested by researchers to combat these malicious threats. Hard to test nets in any logic circuit are the most vulnerable to insertion of Hardware Trojans. Testability analysis is the process of identification of these hard to test nets in a logic circuit. Testability analysis is achieved through the testability metrics namely controllability and observability. Testability metrics can be used as a yardstick in devising efficient Hardware Trojan detection methods. The crux of this study is a novel method for identification of susceptible nets that are prone to Hardware Trojan insertions in a logic circuit. The study also presents a comprehensive analysis of the impact on testability parameters as a result of Hardware Trojans in the identified susceptible nets. The method utilises the testability parameters of nets to define threshold values for isolating susceptible nets in a design. The study details out the impact of the number of trigger inputs as well as the distribution of trigger nets on the testability metrics of digital circuits.

[1]  Mark Mohammad Tehranipoor,et al.  A Novel Technique for Improving Hardware Trojan Detection and Reducing Trojan Activation Time , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Farinaz Koushanfar,et al.  A Survey of Hardware Trojan Taxonomy and Detection , 2010, IEEE Design & Test of Computers.

[3]  Hassan Salmani,et al.  COTD: Reference-Free Hardware Trojan Detection and Recovery Based on Controllability and Observability in Gate-Level Netlist , 2017, IEEE Transactions on Information Forensics and Security.

[4]  Michael S. Hsiao,et al.  Hardware Trojan Attacks: Threat Analysis and Countermeasures , 2014, Proceedings of the IEEE.

[5]  Hassan Salmani,et al.  Vulnerability Analysis of a Circuit Layout to Hardware Trojan Insertion , 2016, IEEE Transactions on Information Forensics and Security.

[6]  Ahmad Patooghy,et al.  Circuit enclaves susceptible to hardware Trojans insertion at gate-level designs , 2018, IET Comput. Digit. Tech..

[7]  John D. Villasenor,et al.  A System-On-Chip Bus Architecture for Thwarting Integrated Circuit Trojan Horses , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Mark Mohammad Tehranipoor,et al.  A Novel Built-In Self-Authentication Technique to Prevent Inserting Hardware Trojans , 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.