Leakage-Tolerant Low-Power Wide Fan-in OR Logic Domino Circuit

A leakage-tolerant low-power wide fan-in OR logic domino circuit is presented to decrease the leakage current and to enhance the noise immunity. Primarily, an efficient switching control in keeper network is developed to reduce the switching of keeper transistor in both phases, so that dynamic power and noise immunity can be improved. Further, a diode-connected NMOS transistor in evaluation network is incorporated in series with the footer transistor of standard domino circuits. This significantly decreases the leakage current and charge sharing because of the stacking effect. This reduction in leakage and charge sharing ensures the improvement in the noise margin. Furthermore, a current mirror and feedback NMOS transistors are also employed in the evaluation network to improve the speed of the circuit and fully discharge the dynamic node. The simulation results of proposed domino and reported domino circuits are designed using Spectre simulator under cadence virtuoso models of 45-nm technology which shows the 31% reduction in power dissipation (PD) and 1.53 times improvement in noise immunity at the similar delay compared to the standard domino circuits.