Design and Analysis of a Mesh-based Wireless Network-on-Chip

Network-on-chip (NoC) architecture is regarded as a solution for future on-chip interconnects. However, the performance advantages of conventional NoC architectures are limited by the long latency and high power consumption due to multi-hop long distance communication among processing elements. To solve these limitations, we employed on-chip wireless communication as express links for transferring data so that transfer latency can be reduced. A hybrid NoC architecture utilizing both wired and wireless communication approaches is proposed in this paper. We also devised a deadlock free routing algorithm that is able to make efficient use of the incorporated wireless links. Moreover, simulated annealing optimization techniques were applied to find optimal locations for wireless routers. Cycle-accurate simulation results showed a significant improvement in transfer latency. Area and power consumption analysis demonstrates the feasibility of our proposed NoC architecture.

[1]  Christof Teuscher,et al.  Hybrid wireless network on chip: A new paradigm in multi-core design , 2009, 2009 2nd International Workshop on Network on Chip Architectures.

[2]  Jason Cong,et al.  CMP network-on-chip overlaid with multi-band RF-interconnect , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.

[3]  Partha Pratim Pande,et al.  Design of an Energy-Efficient CMOS-Compatible NoC Architecture with Millimeter-Wave Wireless Interconnects , 2013, IEEE Transactions on Computers.

[4]  Luca P. Carloni,et al.  Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors , 2008, IEEE Transactions on Computers.

[5]  Mau-Chung Frank Chang,et al.  Terahertz CMOS Frequency Generator Using Linear Superposition Technique , 2008, IEEE Journal of Solid-State Circuits.

[6]  Li-Shiuan Peh,et al.  Polaris: A System-Level Roadmap for On-Chip Interconnection Networks , 2006, 2006 International Conference on Computer Design.

[7]  K.K. O,et al.  On-chip wireless interconnection with integrated antennas , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[8]  Chih-Ming Hung,et al.  A 410GHz CMOS Push-Push Oscillator with an On-Chip Patch Antenna , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[9]  Chifeng Wang,et al.  A Wireless Network-on-Chip Design for Multicore Platforms , 2011, 2011 19th International Euromicro Conference on Parallel, Distributed and Network-Based Processing.

[10]  Partha Pratim Pande,et al.  Wireless NoC as Interconnection Backbone for Multicore Chips: Promises and Challenges , 2012, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[11]  Andrew B. Kahng,et al.  ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[12]  Yi Wang,et al.  SD-MAC: Design and Synthesis of a Hardware-Efficient Collision-Free QoS-Aware MAC Protocol for Wireless Network-on-Chip , 2008, IEEE Transactions on Computers.

[13]  Christof Teuscher,et al.  Scalable Hybrid Wireless Network-on-Chip Architectures for Multicore Systems , 2011, IEEE Transactions on Computers.

[14]  Jason Cong,et al.  A scalable micro wireless interconnect structure for CMPs , 2009, MobiCom '09.

[15]  L. Sekaric,et al.  Ultra-compact, low RF power, 10 Gb/s silicon Mach-Zehnder modulator. , 2007, Optics express.

[16]  William J. Dally,et al.  Deadlock-Free Message Routing in Multiprocessor Interconnection Networks , 1987, IEEE Transactions on Computers.

[17]  Jason Cong,et al.  RF interconnects for communications on-chip , 2008, ISPD '08.

[18]  Eby G. Friedman,et al.  3-D Topologies for Networks-on-Chip , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[19]  A. Sugavanam,et al.  On-chip antennas in silicon ICs and their application , 2005, IEEE Transactions on Electron Devices.

[20]  C. D. Gelatt,et al.  Optimization by Simulated Annealing , 1983, Science.

[21]  Luca Benini,et al.  Networks on chip: a new paradigm for systems on chip design , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[22]  Partha Pratim Pande,et al.  Performance evaluation of wireless networks on chip architectures , 2009, 2009 10th International Symposium on Quality Electronic Design.