论文信息 - A 0.65V, 1.9mW CMOS low-noise amplifier at 5GHz

A 0.65V, 1.9mW CMOS low-noise amplifier at 5GHz

An ultra low-voltage (0.65 V), 5 GHz low noise amplifier (LNA) has been designed, laid out and simulated using Spectre simulator in a standard TSMC 0.18/spl mu/m CMOS technology. The proposed LNA achieves better performance than conventional cascode topology and are confirmed by simulation results. The LNA provides a high gain of 20 dB, a noise figure of 1.4 dB, power dissipation of 1.9 mW from a 0.65 V power supply. To the best of author's knowledge this is the lowest voltage supply CMOS LNA design reported to date.

Krzysztof Iniewski | Yanjie Wang | M. Zamin Khan

[1] Robert W. Dutton,et al. A noise optimization technique for integrated low-noise amplifiers , 2002, IEEE J. Solid State Circuits.

[2] Mourad N. El-Gamal,et al. Very low-voltage (0.8V) CMOS receiver frontend for 5 GHz RF applications , 2002 .

[3] Sayfe Kiaei,et al. A new method to stabilize high frequency high gain CMOS LNA , 2003, 10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003.

[4] Chenming Hu,et al. Future CMOS scaling and reliability , 1993, Proc. IEEE.

[5] Z. Li. Packaged single-ended CMOS low noise amplifier with 2.3 dB noise figure and 64 dBm IIP2 , 2004 .

[6] T.H. Lee,et al. A 1.5 V, 1.5 GHz CMOS low noise amplifier , 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.

[7] Sang-Gug Lee,et al. A 5.2GHz LNA in 0.35µm CMOS utilizing inter–stage series resonance and optimizing the substrate resistance , 2002 .

[8] M. Steyaert,et al. High-performance 5.2 GHz LNA with on-chip inductor to provide ESD protection , 2001 .