FPGA Design and Implementation of MIMO Decoder for 1 Gbps Wireless LAN

This paper presents a high throughput pipeline decoder architecture for multiple input multiple output (MIMO) with good performance and its field programmable gate array (FPGA) implementation. This enhanced pipeline decoder architecture can handle large amounts of data and is suitable for very high throughput system. Based on the proposed architecture, the pipeline decoder architecture has been implemented on Xilinx Virtex5 SX95T FPGA. The results show that when signal-to-noise ratio (SNR) is higher than 25dB, the architecture can achieve a throughput up to 1.16Gbps with bit error rate (BER) lower than 10-6.

[1]  David Tse,et al.  Fundamentals of Wireless Communication , 2005 .

[2]  K.-D. Kammeyer,et al.  MMSE extension of V-BLAST based on sorted QR decomposition , 2003, 2003 IEEE 58th Vehicular Technology Conference. VTC 2003-Fall (IEEE Cat. No.03CH37484).

[3]  Xin Song,et al.  Improved QR Decomposition-Based SIC Detection Algorithm for MIMO System , 2013 .

[4]  D. Perels,et al.  ASIC implementation of a MIMO-OFDM transceiver for 192 Mbps WLANs , 2005, Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005..

[5]  Markus Rupp,et al.  Prototype experience for MIMO BLAST over third-generation wireless system , 2003, IEEE J. Sel. Areas Commun..

[6]  Andreas Peter Burg,et al.  K-best MIMO detection VLSI architectures achieving up to 424 Mbps , 2006, 2006 IEEE International Symposium on Circuits and Systems.