A macromodel technique for VLSI dynamic simulation by mapping pre-characterized transitions
暂无分享,去创建一个
[1] Ivan E. Sutherland,et al. Logical effort: designing for speed on the back of an envelope , 1991 .
[2] N. Evmorfopoulos,et al. Precise Identification of the Worst-Case Voltage Drop Conditions in Power Grid Verification , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.
[3] Chandramouli V. Kashyap,et al. Block-based Static Timing Analysis with Uncertainty , 2003, ICCAD.
[4] Erich Barke,et al. Efficient Modeling Techniques for Dynamic Voltage Drop Analysis , 2007, 2007 44th ACM/IEEE Design Automation Conference.
[5] Andrew B. Kahng,et al. Constructing current-based gate models based on existing timing library , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).
[6] Luca Benini,et al. Analysis of glitch power dissipation in CMOS ICs , 1995, ISLPED '95.
[7] Rajendran Panda,et al. Design and analysis of power distribution networks in PowerPC microprocessors , 1998, DAC.
[8] Wolfgang Nebel,et al. New approach in gate-level glitch modelling , 1996, Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition.