Minimizing Total Power by Simultaneous Assignment

In this paper, we investigate the effectiveness of simul- taneous multiple supply and threshold voltage assignment in mini- mizing the total power static dynamic in generic digital CMOS designs. Achievable power reductions under varying conditions are investigated, including static-power limited designs and sub-1-V processes. Rules-of-thumb are developed for optimal 's and 's to be used in future designs. These models show the optimal second to be approximately half the nominal while the potential total power savings is significantly greater than previ- ously anticipated (60%-65%). We describe the impact of level con- version delays and also demonstrate that the scaling properties of multivoltage systems are very good, particularly when considering impending device scaling advancements. Index Terms—Dual supply voltage, level conversion, power optimization.

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