Active replication: towards a truly SRAM-based FPGA on-line concurrent testing

The reusing of the same hardware resources to implement speed-critical algorithms, without interrupting system operation, is one of the main reasons for the increasing use of reconfigurable computing platforms, employing complex SRAM-based FPGAs. However, new semiconductor manufacturing technologies increase the probability of lifetime operation failures, requiring new on-line testing/fault-tolerance methods able to improve the dependability of the systems where they are included. The Active Replication technique presented in this paper consists of a set of procedures that enables the implementation of a truly non-intrusive structural on-line concurrent testing approach, detecting and avoiding permanent faults and correcting errors due to transient faults. In relation to a previous technique proposed by the authors as part of the DRAFT FPGA concurrent test methodology, the Active Replication technique extends the range of circuits that can be replicated, by introducing a novel method with very low silicon overhead.

[1]  Charles E. Stroud,et al.  BIST-based diagnostics of FPGA logic blocks , 1997, Proceedings International Test Conference 1997.

[2]  Miodrag Potkonjak,et al.  Low overhead fault-tolerant FPGA systems , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[3]  Fabrizio Lombardi,et al.  An Approach for Detecting Multiple Faulty FPGA Logic Blocks , 2000, IEEE Trans. Computers.

[4]  Charles E. Stroud,et al.  Built-in self-test of FPGA interconnect , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[5]  Yervant Zorian,et al.  Testing the Interconnect of RAM-Based FPGAs , 1998, IEEE Des. Test Comput..

[6]  Shantanu Dutt,et al.  Methodologies for Tolerating Cell and Interconnect Faults in FPGAs , 1998, IEEE Trans. Computers.

[7]  Fabrizio Lombardi,et al.  Testing configurable LUT-based FPGA's , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[8]  Miodrag Potkonjak,et al.  On-line fault detection for bus-based field programmable gate arrays , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[9]  Hideo Fujiwara,et al.  Universal Fault Diagnosis for Lookup Table FPGAs , 1998, IEEE Des. Test Comput..

[10]  Gustavo Ribeiro Alves,et al.  DRAFT: an on-line fault detection method for dynamic and partially reconfigurable FPGAs , 2001, Proceedings Seventh International On-Line Testing Workshop.

[11]  Ping Chen,et al.  Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!) , 1996, Proceedings of 14th VLSI Test Symposium.

[12]  Edward J. McCluskey,et al.  A memory coherence technique for online transient error recovery of FPGA configurations , 2001, FPGA '01.

[13]  Yervant Zorian,et al.  RAM-based FPGAs: a test approach for the configurable logic , 1998, Proceedings Design, Automation and Test in Europe.

[14]  José M.F. Ferreira,et al.  Dynamic Replication: The Core of a Truly Non-Intrusive SRAM-based FPGA Structural Concurrent Test Methodology , 2002 .

[15]  Rodham E. Tulloss,et al.  The Test Access Port and Boundary Scan Architecture , 1990 .