An Asynchronous Viterbi Decoder for Low-Power Applications

This paper presents a robust and low-power Viterbi Decoder designed based on asynchronous architecture. The design is based upon Quasi Delay Insensitive (QDI) timing model which leads to a robust functionality for the decoder. To lower the power consumption of the decoder further, an optimization technique to reduce the power dissipation is applied to add-compare-select (ACS) unit of the decoder. The simulation results shows a 20% reduction in the power consumption for the asynchronous design compared to the synchronous design in 0.35μm CMOS technology with a power supply of 2.5V. The throughput for the circuit is 50 MS/s.

[1]  K. Hu,et al.  A Viterbi decoder memory management system using forward traceback and all-path traceback , 1999, 1999 Digest of Technical Papers. International Conference on Consumer Electronics (Cat. No.99CH36277).

[2]  Rix Groenboom,et al.  ASYNCHRONOUS DESIGN METHODOLOGIES , 1993 .

[3]  Scott Hauck,et al.  Asynchronous design methodologies: an overview , 1995, Proc. IEEE.

[4]  Dong Sam Ha,et al.  A low-power Viterbi decoder design for wireless communications applications , 1999, Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454).

[5]  Andrew J. Viterbi,et al.  Error bounds for convolutional codes and an asymptotically optimum decoding algorithm , 1967, IEEE Trans. Inf. Theory.

[6]  Chi-Ying Tsui,et al.  Low power ACS unit design for the Viterbi decoder [CDMA wireless systems] , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[7]  Marios C. Papaefthymiou,et al.  Design of a high-throughput low-power IS95 Viterbi decoder , 2002, DAC '02.

[8]  Alain J. Martin.  Asynchronous datapaths and the design of an asynchronous adder , 1992, Formal Methods Syst. Des..

[9]  Hyun-Ju Park,et al.  A new lower power Viterbi decoder architecture with glitch reduction , 1999, AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360).

[10]  Stephen B. Furber,et al.  A low-power self-timed Viterbi decoder , 2001, Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001.

[11]  Jr. G. Forney,et al.  The viterbi algorithm , 1973 .

[12]  Alain J. Martin.  Programming in VLSI: from communicating processes to delay-insensitive circuits , 1991 .

[13]  A. N. Willson,et al.  A 0.24 mW, 14.4 kbps, r=1/2, K=9 Viterbi decoder , 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.