Response shaper: a novel technique to enhance unknown tolerance for output response compaction

The presence of unknown values in the simulation result is a key barrier to effective output response compaction in practice. This paper proposes a simple circuit module, called a response shaper, to reshape the scan-out responses before feeding them to a space compactor. Along with the proposed reshaping algorithm, response shapers can help the space compactor to reduce the number of undetectable modeled and unmodeled faults in the presence of unknown values. Moreover, the proposed compaction scheme is ATPG-independent and its hardware requirement is pattern-independent. In our experiments, we use a simple XOR compactor as the space compactor to evaluate the effectiveness of the response shaper. The results show that the number of undetectable faults and unobservable scan-out responses can be significantly reduced in comparison with the results of a convolutional compactor. The number of the extra scan-in bits required for the control signals of the response shapers is only a small fraction of the total test data volume. Also, its hardware overhead is acceptable and the runtime of the reshaping algorithm is scalable for large industrial designs.

[1]  Bashir M. Al-Hashimi,et al.  Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression , 2002, DATE.

[2]  Vivek Chickermane,et al.  Channel masking synthesis for efficient on-chip test compression , 2004, 2004 International Conferce on Test.

[3]  Wenjing Rao,et al.  Test application time and volume compression through seed overlapping , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[4]  Sudhakar M. Reddy,et al.  Convolutional compaction of test responses , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[5]  B. Koneman,et al.  LFSR-Coded Test Patterns for Scan Designs , 1993 .

[6]  Salvador Manich,et al.  BIST technique by equally spaced test vector sequences , 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

[7]  Irith Pomeranz,et al.  On efficient X-handling using a selective compaction scheme to achieve high test response compaction ratios , 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

[8]  Huaguo Liang,et al.  Two-dimensional test data compression for scan-based deterministic BIST , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[9]  Subhasish Mitra,et al.  X-compact: an efficient response compaction technique for test cost reduction , 2002, Proceedings. International Test Conference.

[10]  Brion L. Keller,et al.  OPMISR: the foundation for compressed ATPG vectors , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[11]  Irith Pomeranz,et al.  On Compacting Test Response Data Containing Unknown Values , 2003, ICCAD 2003.

[12]  Nur A. Touba,et al.  Scan vector compression/decompression using statistical coding , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[13]  Bernd Becker,et al.  X-masking during logic BIST and its impact on defect coverage , 2006, IEEE Trans. Very Large Scale Integr. Syst..

[14]  Minesh B. Amin,et al.  X-tolerant compression and application of scan-atpg patterns in a bist architecture , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[15]  Irith Pomeranz,et al.  Masking of unknown output values during output response compression by using comparison units , 2004, IEEE Transactions on Computers.