Techniques for Compiler-Directed Cache Coherence

The performance of large scale shared memory multiprocessors can be greatly improved if they can cache remote shared data in the private caches of the processors. However, maintaining cache coherence for such systems remains a challenge. Although hardware directory schemes give good performance, they might be too complicated and expensive for large scale multiprocessors. The article provides a comprehensive guide of an alternative approach, called compiler directed cache coherence techniques. Compiler directed techniques maintain coherence of caches locally by individual processors, eliminating the need for directory hardware and interprocessor communication. We survey the state of the art software and hardware compiler directed techniques and discuss the basic concepts and issues. We also demonstrate the feasibility and performance of compiler directed cache coherence by presenting a case study of the Two Phase Invalidation scheme.