A fast radix-3 SAR analog-to-digital converter

This paper presents a new radix-3 successive approximation register (SAR) analog-to-digital converter (ADC). Our proposed radix-3 SAR ADC can generate 1.6N binary bits during N comparison cycles. The radix-3 SAR ADC is 60% faster than the conventional radix-2 SAR ADC. Our prototypes are implemented with 4 and 7 ternary bits using 180nm CMOS technology. They can achieve a signal-to-quantization-noise ratio (SQNR) of 39 dB and 66 dB which are equivalent to 6.2 and 10.7 binary bits respectively.

[1]  Ho-Jin Park,et al.  An 8.6 ENOB 900MS/s time-interleaved 2b/cycle SAR ADC with a 1b/cycle reconfiguration for resolution enhancement , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[2]  Lane Brooks,et al.  Circuits and algorithms for pipelined ADCs in scaled CMOS technologies , 2008 .

[3]  David A. Johns,et al.  Analog Integrated Circuit Design , 1996 .

[4]  P. Gray,et al.  All-MOS charge redistribution analog-to-digital conversion techniques. I , 1975, IEEE Journal of Solid-State Circuits.

[5]  D.A. Hodges,et al.  A self-calibrating 15 bit CMOS A/D converter , 1984, IEEE Journal of Solid-State Circuits.

[6]  Zhiheng Cao,et al.  A 32 mW 1.25 GS/s 6b 2b/Step SAR ADC in 0.13$\ \mu$m CMOS , 2009, IEEE Journal of Solid-State Circuits.

[7]  Shouli Yan,et al.  A 32 mW 1.25 GS/s 6b 2b/Step SAR ADC in 0.13 µm CMOS , 2009, IEEE J. Solid State Circuits.

[8]  Bertan Bakkaloglu,et al.  A radix-3 SAR analog-to-digital converter , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.