Numerical modeling and characterization of the stress migration behaviour upon various 90 nanometer Cu/Low k interconnects

Stress migration (SM) behavior found on various Cu/Low k interconnects is analyzed in this article. The simulation results demonstrate that the minimum stresses always occur on/near via bottom, which makes the dummy via insertion an effect way relieving SM induced circuit failure. A numerical index reflecting the bulk vacancy density evolution is developed from the simulated stress distribution and aimed at predicting the destination of the migrating vacancies driven by the thermally generated stress gradient of the interconnect system. Though still in its burgeoning stage, the simulated SM behavior using the index compared well against those experimentally collected data.