A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure

An 8b 1GS/s ADC is presented that interleaves two 2b/cycle SARs. To enhance speed and save power, the prototype utilizes segmentation switching and custom-designed DAC array with high density in a low parasitic layout structure. It operates at 1GS/s from 1V supply without interleaving calibration and consumes 3.8mW of power, exhibiting a FoM of 24fJ/conversion step. The ADC occupies an active area of 0.013mm2 in 65nm CMOS including on-chip offset calibration.

[1]  Rui Paulo Martins,et al.  A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS , 2011, IEEE Asian Solid-State Circuits Conference 2011.

[2]  Hidemi Noguchi,et al.  A 22-mW 7b 1.3-GS/s pipeline ADC with 1-bit/stage folding converter architecture , 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

[3]  L. Richard Carley,et al.  A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP digital CMOS , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[4]  Wei-Hsuan Tu,et al.  A 1.2V 30mW 8b 800MS/s time-interleaved ADC in 65nm CMOS , 2008, 2008 IEEE Symposium on VLSI Circuits.

[5]  Yung-Hui Chung,et al.  A 16-mW 8-Bit 1-GS/s subranging ADC in 55nm CMOS , 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.