On the design of self-checking boundary scannable boards

In this paper the Boundary Scan technique and the Un@ed Built-In Self-Test scheme are combined in order to propose a strategy suitable for the manufacturing, the field testing and the concurrent error detection on integrated circuits and board interconnects. Such unification of the off-line and the on-line testing plays a major role in the design for broad testability of self-checking boards. This unified test strategy is primarily aimed at critical application designs: transportation systems, nuclear plants, etc.. ., which are the main targets. This architecture, oriented primarily towards the off-line test, provides efficient means of testing of circuits and board interconnects. The association of BIST and BS techniques leads to a significant reduction of the automatic test equipment complexity, due to lower memory requirements and weaker test time constraints. The other part of the tests necessary for circuits and boards is related to the on-line testing capability, a feature of great importance for systems where poor functioning can, for example, lead to a disaster. This is the case of railway, automotive and nuclear systems, where errors must be detected before they contaminate other units and at a point where basic repair is still possible. The self-checking circuit implementation, for making on-line testing possible, is based on the encoding of functional block outputs and on the verification of

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