Study of impact of BTI's local layout effect including recovery effect on various standard-cells in 10nm FinFET

This paper presents an analysis methodology of the impact of Local Layout Effect (LLE) of bias temperature instability (BTI) on logic circuits by measuring Ring-Oscillators (RO) consist of many kinds of standard cells and shows its measurement result in a 10nm FinFET process. The measured delay degradations of all ROs are well correlated with estimated one without considering LLE of BTI and its maximum error rates is −16% and +13%. The LLE on BTI recovery effect is also evaluated and there is no obvious standard cell type dependency. This analysis would be useful for more accurate guideline to design BTI guard-band on logic circuits for high reliability required applications.

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