Load distribution with the proximity congestion awareness in a network on chip

In networks on chip (NoC) very low cost and high performance switches are of critical importance. For a regular two-dimensional NoC, we propose a very simple, memoryless switch. In the case of congestion, packets are emitted in a non-ideal direction, also called deflective routing. To increase the maximum tolerable load of the network, we propose a proximity congestion awareness (PCA) technique, where switches use the load information of neighbouring switches, called stress values, for their own switching decisions, thus avoiding congested areas. We present simulation results with random traffic which show that the PCA technique can increase the maximum traffic load by a factor of over 20.

[1]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[2]  Axel Jantsch,et al.  A network on chip architecture and design methodology , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

[3]  William Stallings,et al.  Data and Computer Communications , 1985 .

[4]  Tughrul Arslan,et al.  Proceedings Design, Automation and Test in Europe Conference and Exhibition , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[5]  William J. Dally,et al.  The torus routing chip , 2005, Distributed Computing.

[6]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .