Memory Management of Large Data Sets in Volume Visualization Systems

Significant improvements in hardware components result in the potential to process and render large volumes with complex features and interactions. This has challenged system developers to manage several gigabytes of memory at interactive rates. Ray casting a 1024 volume with 2 bytes/voxel in 30Hz requires memory bandwidth of 60GB/sec. Some of the volumetric system design issues are: time to market, scalability, component costs and physical layout. Some parallel processing strategies include distributed systems, algorithmic optimizations, levying graphics accelerator hardware, and designing volumetric accelerator hardware. Distributed systems use relatively cheap off the shelf computers networked together. With networking hardware speeds exceeding 1Gb/sec it has become feasible to distribute very large data sets among several PCs to manipulate and render in real time. Graphics accelerator texture mapping is used for the compositing phase of many algorithms, but it limits the quality achievable. Some algorithmic improvements can be implemented by the operating system or in hardware. SIMD arrays are appropriate for volume designs because most operations are repeated on vast amounts of data. In any of these solutions, memory management is critical. A memory bandwidth bottleneck is when the processors stall frequently to wait for memory fetches. Studies indicate that dividing the volume into sub-volumes that are distributed among the processing elements reduces view dependence. Inherent with this approach is the need for balanced load distribution. Multi level caching allows implementation of smaller L1 caches. In this paper I describe the memory bandwidth bottleneck problem and some of the decisions that are made when designing a volume rendering architecture. In addition I give an overview of some of the most well-known volume rendering algorithms and well established optimizations, and a description of some previous work on volume architectures, work to date on the Cube-5 architectures and the potential to improve cache scheduling for ray tracing based on the on ray dependency graph. Topics of Discussion

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