Mastering the Art of High Mobility Material Integration on Si: A Path towards Power-Efficient CMOS and Functional Scaling

In this work, we will review the current progress in integration and device design of high mobility devices. With main focus on (Si)Ge for PMOS and In(Ga)As for NMOS, the benefits and challenges of integrating these materials on a Si platform will be discussed for both density scaling (“more Moore”) and functional scaling to enhance on-chip functionality (“more than Moore”).

[1]  M. Ida,et al.  Over 300 GHz f/sub T/ and f/sub max/ InP/InGaAs double heterojunction bipolar transistors with a thin pseudomorphic base , 2002, IEEE Electron Device Letters.

[2]  M. J. W. Rodwell,et al.  Record Ion (0.50 mA/µm at VDD = 0.5 V and Ioff = 100 nA/µm) 25 nm-gate-length ZrO2/InAs/InAlAs MOSFETs , 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

[3]  P. Kirsch,et al.  Self-aligned III-V MOSFETs heterointegrated on a 200 mm Si substrate using an industry standard process flow , 2010, 2010 International Electron Devices Meeting.

[4]  Peter Chen,et al.  50-nm E-mode In0.7Ga0.3As PHEMTs on 100-mm InP substrate with fmax > 1 THz , 2010, 2010 International Electron Devices Meeting.

[5]  B. Kaczer,et al.  Characterization of self-heating in high-mobility Ge FinFET pMOS devices , 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

[6]  D. Caimi,et al.  An InGaAs on Si platform for CMOS with 200 mm InGaAs-OI substrate, gate-first, replacement gate planar and FinFETs down to 120 nm contact pitch , 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

[7]  M. J. W. Rodwell,et al.  Record extrinsic transconductance (2.45 mS/µm at VDS = 0.5 V) InAs/In0.53Ga0.47As channel MOSFETs using MOCVD source-drain regrowth , 2013, 2013 Symposium on VLSI Technology.

[8]  P. Ye,et al.  First experimental demonstration of 100 nm inversion-mode InGaAs FinFET through damage-free sidewall etching , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[9]  G. Dewey,et al.  High mobility strained germanium quantum well field effect transistor as the p-channel device option for low power (Vcc = 0.5 V) III–V CMOS architecture , 2010, 2010 International Electron Devices Meeting.

[10]  S. Datta,et al.  Indium arsenide (InAs) single and dual quantum-well heterostructure FinFETs , 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

[11]  H. Mertens,et al.  BTI reliability of advanced gate stacks for Beyond-Silicon devices: Challenges and opportunities , 2014, 2014 IEEE International Electron Devices Meeting.

[12]  L. Witters,et al.  Strained germanium quantum well p-FinFETs fabricated on 45nm Fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect , 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

[13]  Shimeng Yu,et al.  Device and system level design considerations for analog-non-volatile-memory based neuromorphic architectures , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

[14]  R. Rooyackers,et al.  In0.53Ga0.47As quantum-well MOSFET with source/drain regrowth for low power logic applications , 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

[15]  Thomas Schroeder,et al.  Invited) Epitaxial Growth of Low Defect SiGe Buffer Layers for Integration of New Materials on 300 mm Silicon Wafers , 2013 .

[16]  Dimitri A. Antoniadis,et al.  A new self-aligned quantum-well MOSFET architecture fabricated by a scalable tight-pitch process , 2013, 2013 IEEE International Electron Devices Meeting.

[17]  J. Bucchignano,et al.  High-Performance $\hbox{In}_{0.7}\hbox{Ga}_{0.3}\hbox{As}$ -Channel MOSFETs With High-$\kappa$ Gate Dielectrics and $\alpha$-Si Passivation , 2009, IEEE Electron Device Letters.

[18]  C. Merckling,et al.  An InGaAs/InP quantum well finfet using the replacement fin process integrated in an RMG flow on 300mm Si substrates , 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

[19]  B. Duriez,et al.  Scaled p-channel Ge FinFET with optimized gate stack and record performance integrated on 300mm Si wafers , 2013, 2013 IEEE International Electron Devices Meeting.

[20]  N. Taoka,et al.  1-nm-thick EOT high mobility Ge n- and p-MOSFETs with ultrathin GeOx/Ge MOS interfaces fabricated by plasma post oxidation , 2011, 2011 International Electron Devices Meeting.

[21]  Aaron Thean,et al.  Impact of the channel thickness on the performance of ultrathin InGaAs channel MOSFET devices , 2013, 2013 IEEE International Electron Devices Meeting.

[22]  L.-E. Wernersson,et al.  Vertical Enhancement-Mode InAs Nanowire Field-Effect Transistor With 50-nm Wrap Gate , 2008, IEEE Electron Device Letters.

[23]  W. E. Hoke,et al.  Monolithic integration of silicon CMOS and GaN transistors in a current mirror circuit , 2012 .

[24]  Gengchiau Liang,et al.  Gate-all-around CMOS (InAs n-FET and GaSb p-FET) based on vertically-stacked nanowires on a Si platform, enabled by extremely-thin buffer layer technology and common gate stack and contact modules , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

[25]  B. Duriez,et al.  InAs N-MOSFETs with record performance of Ion = 600 μA/μm at Ioff = 100 nA/μm (Vd = 0.5 V) , 2013, 2013 IEEE International Electron Devices Meeting.

[26]  Paul Zimmerman,et al.  Thin epitaxial si films as a passivation method for Ge(100) : Influence of deposition temperature on ge surface segregation and the high-k/Ge interface quality , 2006 .

[27]  Massimo Alioto,et al.  Understanding the Potential and the Limits of Germanium pMOSFETs for VLSI Circuits From Experimental Measurements , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[28]  Ali Khakifirooz,et al.  First demonstration of high-Ge-content strained-Si1−xGex (x=0.5) on insulator PMOS FinFETs with high hole mobility and aggressively scaled fin dimensions and gate lengths for high-performance applications , 2014, 2014 IEEE International Electron Devices Meeting.

[29]  Massimo Alioto,et al.  Buried Silicon-Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits Under Aggressive Voltage Scaling , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[30]  M. Heyns,et al.  Quantification of Drain Extension Leakage in a Scaled Bulk Germanium PMOS Technology , 2009, IEEE Transactions on Electron Devices.

[31]  A. Hikavyy,et al.  85nm-wide 1.5mA/µm-ION IFQW SiGe-pFET: Raised vs embedded Si0.75Ge0.25 S/D benchmarking and in-depth hole transport study , 2012, 2012 Symposium on VLSI Technology (VLSIT).

[32]  Tomonori Nishimura,et al.  Direct Evidence of GeO Volatilization from GeO2/Ge and Impact of Its Suppression on GeO2/Ge Metal–Insulator–Semiconductor Characteristics , 2008 .

[33]  Andre Stesmans,et al.  A first-principles study of the structural and electronic properties of III-V/thermal oxide interfaces , 2009 .

[34]  An Steegen Technology innovation in an IoT Era , 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

[35]  M. Y. Simmons,et al.  Quantum computing in silicon , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

[36]  Darin Leonhardt,et al.  Effect of threading dislocation density and dielectric layer on temperature-dependent electrical characteristics of high-hole-mobility metal semiconductor field effect transistors fabricated from wafer-scale epitaxially grown p-type germanium on silicon substrates , 2014 .

[37]  D. Caimi,et al.  Confined Epitaxial Lateral Overgrowth (CELO): A novel concept for scalable integration of CMOS-compatible InGaAs-on-insulator MOSFETs on large-area Si substrates , 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

[38]  A. Vais,et al.  Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200μS/μm at 50nm Lg using a replacement Fin RMG flow , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

[39]  Kang Yang,et al.  Envelope Tracking RF Power Amplifiers: Fundamentals, Design Challenges, and Unique Opportunities Offered by LEES-SMART InGaAs-on-CMOS Process , 2016 .

[40]  E. Lind,et al.  High transconductance self-aligned gate-last surface channel In0.53Ga0.47As MOSFET , 2011, 2011 International Electron Devices Meeting.

[41]  Shinichi Takagi,et al.  Characterization of 7-nm-thick strained Ge-on-insulator layer fabricated by Ge-condensation technique , 2003 .

[42]  S. Takagi,et al.  CMOS integration of InGaAs nMOSFETs and Ge pMOSFETs with self-align Ni-based metal S/D using direct wafer bonding , 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

[43]  M. A. Pourghaderi,et al.  RTN and PBTI-induced time-dependent variability of replacement metal-gate high-k InGaAs FinFETs , 2014, 2014 IEEE International Electron Devices Meeting.

[44]  J. Kwo,et al.  GaAs MOSFET with oxide gate dielectric grown by atomic layer deposition , 2003, IEEE Electron Device Letters.

[45]  Marc Heyns,et al.  Electrical Properties of III-V/Oxide Interfaces , 2009 .

[46]  S. Takagi,et al.  CMOS photonics technologies based on heterogeneous integration of SiGe/Ge and III-V on Si , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

[47]  C. H. Chen,et al.  In0.53Ga0.47As MOSFETs with high channel mobility and gate stack quality fabricated on 300 mm Si substrate , 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

[48]  A. Brand,et al.  15nm-WFIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process , 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

[49]  Niamh Waldron,et al.  (Invited) Selective-Area Metal Organic Vapor-Phase Epitaxy of InGaAs/InP Heterostrucures on Si for Advanced CMOS Devices , 2014 .

[50]  Lukas Czornomaz,et al.  First RF characterization of InGaAs replacement metal gate (RMG) nFETs on SiGe-OI FinFETs fabricated by 3D monolithic integration , 2016 .

[51]  Bin Tian,et al.  Room-temperature InP distributed feedback laser array directly grown on silicon , 2015 .

[52]  Donghyun Kim,et al.  High-mobility low band-to-band-tunneling strained-Germanium double-gate heterostructure FETs: Simulations , 2006, IEEE Transactions on Electron Devices.

[53]  G. Dewey,et al.  Advanced high-K gate dielectric for high-performance short-channel In0.7Ga0.3As quantum well field effect transistors on silicon substrate for low power logic applications , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[54]  A. Gnudi,et al.  Comprehensive comparison and experimental validation of band-structure calculation methods in III-V semiconductor quantum wells , 2016 .

[55]  L. Witters,et al.  Strained Germanium quantum well pMOS FinFETs fabricated on in situ phosphorus-doped SiGe strain relaxed buffer layers using a replacement Fin process , 2013, 2013 IEEE International Electron Devices Meeting.

[56]  Hyunhyub Ko,et al.  Ultrathin compound semiconductor on insulator layers for high-performance nanoscale transistors , 2010, Nature.

[57]  Niamh Waldron,et al.  InGaAs Gate-All-Around Nanowire Devices on 300mm Si Substrates , 2014, IEEE Electron Device Letters.