Level Converting Scan Flip-Flop

Clustered voltage scaling (CVS) is an effective way to decrease power dissipation in nanoscale circuit design. One of the design challenges in the CVS is the design of an efficient level converting flip-flop with fewer power and delay overheads. In this paper, we present the static level converting scan flip-flop (SLCSFF), which employs clock and power gating during idle mode to eliminate dynamic power and reduce static power, while retaining its state. The dual-edge triggering capability is achieved by using a dual pulse clock generator that generates short pulses at both rising and falling edges of the clock. Based on simulation results in a 45nm CMOS technology, the proposed level converting scan flip-flop outperforms the existing ones by 56%-75% in terms of Power-Delay Product (PDP).