论文信息 - SPICE modeling and quick estimation of MOSFET mismatch based on BSIM3 model and parametric tests

SPICE modeling and quick estimation of MOSFET mismatch based on BSIM3 model and parametric tests

This paper reports a MOS transistor mismatch model applicable for submicron CMOS technologies and developed based on the industry standard BSLM3v3 model. A simple and unified expression was derived to formulate the effect of MOSFET mismatch on drain current variance. A way to quickly estimate the drain current mismatch was also suggested. The model has been integrated into HSPICE, and results obtained from simulation and measurements were compared.

Juin J. Liou | Qingwen Zhang | J. Thomson | P. Layman | J. R. McMacken

[1] C.C. McAndrew,et al. A comprehensive MOSFET mismatch model , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[2] M.J.M. Pelgrom,et al. Matching properties of MOS transistors , 1989 .

[3] K. R. Lakshmikumar,et al. Characterisation and modeling of mismatch in MOS transistors for precision analog design , 1986 .

[4] Mohammed Ismail,et al. Statistical modeling of device mismatch for analog MOS integrated circuits , 1992 .

[5] W. Sansen,et al. Mismatch Characterization of Submicron MOS Transistors , 1997 .

[6] J.J. Liou,et al. Modeling of mismatch effect in submicron MOSFETs based on BSIM3 model and parametric tests , 2001, IEEE Electron Device Letters.

[7] T. Serrano-Gotarredona,et al. Systematic Width-and-Length Dependent CMOS Transistor Mismatch Characterization and Simulation , 1999 .