Thermal Design Considerations for COB Applications

As requirements for system performance and density increase, more attention is being given to chip‐on‐board (COB) packaging techniques. COB is ‘surface mount packaging taken to the extreme’ as it involves the direct mounting of bare semiconductor die to printed circuit board substrates. In this paper, the ‘thermal resistance’ of a single COB package is proposed. An analytical model for this resistance is developed for a multilayer board configuration using a combination of Fourier transform and adjoint‐solution techniques. Parameters in the model include the chip and board geometric parameters, individual layer unit conductances, and top and bottom surface film coefficients. A series of curves are developed from the model. These curves may be used in the initial design process to determine, for example, required film coefficients and the efficacy of adding thermal planes to the board. The model is also used to test the adequacy of the ‘effective series conductivity’ of a multilayer board.