A Heterogeneous Hypercube Based On Strengthened Nodes For A Fast Processing Of SAR Raw-data

A family of high performance processing elements has been conceived to implement flexible multiprocessor structures for real-time applications. The floating-point capabilities of the INMOS transputer components (T222-T805) have been improved, by using the AT&T floating-point Digital Signal Processors (DSP32-DSP32C), allowing to achieve up to 25 MFLOPS, 30 MIPS. In the paper, the design of a single board T800/DSP-32C based is presented and the simulation results of its specialization in signal processing applications are also reported. A comparative test between the traditional Cooley-Tukey FFT Algorithm (aA) and the Prime Factor Algorithm (PFA) shows that a 4096 complex points radix 4-CTA takes 16.6 ms. while for a 5040 complex points PFA about 32.3 ms are needed. A flexible development system has been also realized to allow a careful design of various "Strengthened Nodes", since it can be used as test-bed to compare the performance of different DSPs available on the market, when they are connected to components of the transputer family. "Strengthened Nodes" will be used in heterogeneous multiprocessor structures specialized for Synthetic Aperture Radar (SAR) data processing.