A Novel Power Optimization Method by Minimum Comparator Number Algorithm for Pipeline ADCs
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[1] Bjørnar Hernes,et al. A cost-efficient high-speed 12-bit pipeline ADC in 0.18-μm digital CMOS , 2005 .
[2] P.R. Gray,et al. A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR , 2004, IEEE Journal of Solid-State Circuits.
[3] J. Bjornsen,et al. A cost-efficient high-speed 12-bit pipeline ADC in 0.18-/spl mu/m digital CMOS , 2005, IEEE Journal of Solid-State Circuits.
[4] Stephen H. Lewis,et al. Optimizing the stage resolution in pipelined, multistage, analog-to-digital converters for video-rate applications , 1992 .
[5] Howard C. Luong,et al. Power optimization for pipeline analog-to-digital converters , 1999 .
[6] Randall L. Geiger,et al. An architecture and an algorithm for fully digital correction of monolithic pipelined ADCs , 1995 .