Power and area efficient CORDIC-Based DCT using direct realization of decomposed matrix

Abstract Discrete Cosine Transform (DCT) is one of the most fundamental yet complicated transforms in image and signal processing. In spite of the diverse applications of DCT, its implementation is still considered as a great difficulty due to high computational complexity and large power consumption. In this paper, a novel CORDIC-based DCT architecture is developed which remarkably reduces power consumption, area overhead, and hardware complexity. The key idea behind the proposed architecture is that the fundamental data path components of DCT are individually modified with incremental advance on butterfly block, CORDIC array, and controller unit by means of matrix decomposition, resource sharing and merging techniques, removal of pre-processing step, extending CORDIC idle time, and deploying the Low-power Lookahead (LPLA) CORDIC structure. Also, in the proposed controller unit, switching activity is reduced by changing the generation order of the butterfly outputs. In addition, the proposed structure has regular, scalable, and modular architecture which makes it a suitable candidate for hardware implementation.