An Edge-endpoint-based Configurable Hardware Architecture for VLSI Layout Design Rule Checking

Previous efforts to build hardware accelerators for VLSI layout Design Rule Checking (DRC) were hobbled by the fact that it is often impractical to build a different rulechecking ASIC each time design rules or fabrication processes change. In this paper, we propose a configurable hardware approach to DRC. It can garner impressive speedups over software approaches, while retaining the flexibility needed to change the rule checker as rules or processes change.

[1]  Sartaj Sahni,et al.  A Systolic Design-Rule Checker , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  Christopher J. Van Wyk,et al.  Space Efficient Algorithms for VLSI Artwork Analysis , 1983, 20th Design Automation Conference Proceedings.

[3]  Ulrich Lauther.  An O (N log N) Algorithm for Boolean Mask Operations , 1981, 18th Design Automation Conference.

[4]  Rob A. Rutenbar,et al.  A Scanline Data Structure Processor for VLSI Geometry Checking , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Andrew R. Pleszkun,et al.  An Algorithm for Design Rule Checking on a Multiprocessor , 1985, 22nd ACM/IEEE Design Automation Conference.

[6]  Larry Seiler.  A Hardware Assisted Design Rule Check Architecture , 1982, DAC 1982.

[7]  Wray L. Buntine,et al.  Design rule checking and analysis of IC mask designs , 1976, DAC '76.

[8]  Clark Marshall Baker.  Artwork Analysis Tools for VLSI Circuits. , 1980 .

[9]  Steven M. Rubin,et al.  Computer Aids For VLSI Design , 1987 .