Unequal error protection with CRC-16 bits in EPC class-1 generation-2 UHF RFID systems

This paper deals with cyclic-redundancy-check (CRC) bits stored in the memory of tags of electronic product code (EPC) class-1 generation-2 UHF radio-frequency identification (RFID) systems. It is shown that tag memory bits transmitted via backscattering to a reader have two levels of error protection. The structure and properties of the underlying binary linear unequal-error-protection (UEP) (128,112,4) code are studied. The amount of redundancy provided by the 16 CRC bits is shown to be sufficient for the decoder in the reader to correct all single-bit errors and 79% of all possible double-bit errors. Moreover, the number of tag memory bits with additional error protection as well as the structure of the associated correctable error patterns are established.

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