Toward Formal Design of Practical Cryptographic Hardware Based on Galois Field Arithmetic

This paper presents a formal method for designing cryptographic processor datapaths on the basis of arithmetic circuits over Galois fields (GFs). The proposed method describes GF arithmetic circuits in the form of hierarchical graph structures, where nodes represent sub-circuits whose functions are defined by arithmetic formulae over GFs, and edges represent data dependency between nodes. In this paper, we first introduce the application of graph representation to arithmetic circuits over extension fields of \mbi GF(\mbi p\mbi m) (\mbi p ≥ 2) and composite fields, which are commonly used in the design of cryptographic processors. The newly proposed graph representation can be formally verified through symbolic computation techniques based on polynomial reduction and Gröbner basis. We then demonstrate the capabilities of the proposed approach through an experimental design of a 128-bit AES (Advanced Encryption Standard) datapath including multiplicative inversion circuits over the composite field \mbi GF(((22)2)2). The results show that the proposed method can describe such practical datapaths, as well as that complete verification of such a datapath can be carried out within a short period of time.

[1]  Ç. Koç,et al.  Finite field arithmetic for cryptography , 2010, IEEE Circuits and Systems Magazine.

[2]  Berk Sunar,et al.  Constructing Composite Field Representations for Efficient Conversion , 2003, IEEE Trans. Computers.

[3]  Rolf Drechsler,et al.  Advanced Formal Verification , 2004 .

[4]  Matthew J. B. Robshaw,et al.  Essential Algebraic Structure within the AES , 2002, CRYPTO.

[5]  Nigel P. Smart,et al.  Hardware Implementation of Finite Fields of Characteristic Three , 2002, CHES.

[6]  Eli Biham,et al.  Bug Attacks , 2008, CRYPTO.

[7]  Toshiyuki Yamane,et al.  Towards Efficient Verification of Arithmetic Algorithms over Galois Fields GF(2m) , 2001, CAV.

[8]  Randal E. Bryant,et al.  Verification of Arithmetic Circuits with Binary Moment Diagrams , 1995, 32nd Design Automation Conference.

[9]  Rolf Drechsler,et al.  Circuit design from Kronecker Galois field decision diagrams for multiple-valued functions , 1997, Proceedings 1997 27th International Symposium on Multiple- Valued Logic.

[10]  Sofia Cassel,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 2012 .

[11]  Takeshi Sugawara,et al.  ASIC Performance Comparison for the ISO Standard Block Ciphers , 2007 .

[12]  Akashi Satoh,et al.  An Optimized S-Box Circuit Architecture for Low Power AES Design , 2002, CHES.

[13]  Takafumi Aoki,et al.  A Formal Approach to Designing Cryptographic Processors Based on $GF(2^m)$ Arithmetic Circuits , 2012, IEEE Transactions on Information Forensics and Security.

[14]  Debdeep Mukhopadhyay,et al.  Hierarchical Verification of Galois Field Circuits , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[15]  Niels Ferguson,et al.  A Simple Algebraic Representation of Rijndael , 2001, Selected Areas in Cryptography.