Flikker: saving DRAM refresh-power through critical data partitioning

Energy has become a first-class design constraint in computer systems. Memory is a significant contributor to total system power. This paper introduces Flikker, an application-level technique to reduce refresh power in DRAM memories. Flikker enables developers to specify critical and non-critical data in programs and the runtime system allocates this data in separate parts of memory. The portion of memory containing critical data is refreshed at the regular refresh-rate, while the portion containing non-critical data is refreshed at substantially lower rates. This partitioning saves energy at the cost of a modest increase in data corruption in the non-critical data. Flikker thus exposes and leverages an interesting trade-off between energy consumption and hardware correctness. We show that many applications are naturally tolerant to errors in the non-critical data, and in the vast majority of cases, the errors have little or no impact on the application's final outcome. We also find that Flikker can save between 20-25% of the power consumed by the memory sub-system in a mobile device, with negligible impact on application performance. Flikker is implemented almost entirely in software, and requires only modest changes to the hardware.

[1]  Miodrag Potkonjak,et al.  MediaBench: a tool for evaluating and synthesizing multimedia and communications systems , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.

[2]  Hsien-Hsin S. Lee,et al.  Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).

[3]  Peter M. Chen,et al.  The impact of recovery mechanisms on the likelihood of saving corrupted state , 2002, 13th International Symposium on Software Reliability Engineering, 2002. Proceedings..

[4]  Karthikeyan Sankaralingam,et al.  Relax: an architectural framework for software recovery of hardware faults , 2010, ISCA.

[5]  Lizy Kurian John,et al.  ESKIMO - energy savings using semantic knowledge of inconsequential memory occupancy for DRAM subsystem , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[6]  Joseph A. Catania Soft Errors in Electronic Memory – A White Paper , 2022 .

[7]  Luca Benini,et al.  Energy-Efficient Value Based Selective Refresh for Embedded DRAMS , 2006, J. Low Power Electron..

[8]  Onur Mutlu,et al.  Architecting phase change memory as a scalable dram alternative , 2009, ISCA '09.

[9]  W. Marsden I and J , 2012 .

[10]  Gernot Heiser,et al.  An Analysis of Power Consumption in a Smartphone , 2010, USENIX Annual Technical Conference.

[11]  Yue Wang,et al.  Exploiting Half-Wits: Smarter Storage for Low-Power Devices , 2011, FAST.

[12]  Karthick Rajamani,et al.  Energy Management for Commercial Servers , 2003, Computer.

[13]  Karthik Pattabiraman,et al.  Samurai: protecting critical data in unsafe languages , 2008, Eurosys '08.

[14]  Marios C. Papaefthymiou,et al.  Block-based multiperiod dynamic memory design for low data-retention power , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[15]  David Blaauw,et al.  Opportunities and challenges for better than worst-case design , 2005, ASP-DAC.

[16]  Woongki Baek,et al.  Green: a framework for supporting energy-conscious programming using controlled approximation , 2010, PLDI '10.

[17]  Amin Vahdat,et al.  System Support for Energy Management in Mobile and Embedded Workloads: A White Paper , 1999 .

[18]  Scott Shenker,et al.  Scheduling for reduced CPU energy , 1994, OSDI '94.

[19]  John Sartori,et al.  Fluid NMR-Performing Power/Reliability Tradeoffs for Applications with Error Tolerance , .

[20]  Douglas L. Jones,et al.  GRACE-1: cross-layer adaptation for multimedia quality and battery energy , 2006, IEEE Transactions on Mobile Computing.

[21]  Harish Patil,et al.  Pin: building customized program analysis tools with dynamic instrumentation , 2005, PLDI '05.

[22]  Henry Hoffmann,et al.  Dynamic knobs for responsive power-aware computing , 2011, ASPLOS XVI.

[23]  Trevor Mudge,et al.  Razor: a low-power pipeline based on circuit-level timing speculation , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

[24]  Vicky Wong,et al.  Soft Error Resilience of Probabilistic Inference Applications , 2006 .

[25]  Shekhar Y. Borkar,et al.  Microarchitecture and Design Challenges for Gigascale Integration , 2004, MICRO.

[26]  Donald Yeung,et al.  Application-Level Correctness and its Impact on Fault Tolerance , 2007, 2007 IEEE 13th International Symposium on High Performance Computer Architecture.

[27]  Rong Ge,et al.  High-performance, power-aware distributed computing for scientific applications , 2005, Computer.

[28]  Eric Rotenberg,et al.  Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM , 2006, The Twelfth International Symposium on High-Performance Computer Architecture, 2006..

[29]  Martin Rinard,et al.  Using Code Perforation to Improve Performance, Reduce Energy Consumption, and Respond to Failures , 2009 .

[30]  Paul Johns,et al.  Working Overtime: Patterns of Smartphone and PC Usage in the Day of an Information Worker , 2009, Pervasive.

[31]  Vimal Bhalodia SCALE DRAM subsystem power analysis , 2005 .

[32]  Jason Flinn,et al.  Power and Energy Characterization of the Itsy Pocket Computer (Version 1.5) , 2000 .

[33]  Zhao Wu,et al.  Fault-tolerant refresh power reduction of DRAMs for quasi-nonvolatile data retention , 1999, Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99).

[34]  Philip Levis,et al.  Surviving sensor network software faults , 2009, SOSP '09.

[35]  David Blaauw,et al.  Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation , 2003, MICRO.