MRouter:The Router Based on Memory Centric Mechanism

The interconnection network in parallel systems remains a key issue in high performance computer research. In 1999, we proposed a new interconnection mechanism called MCIM, which is based on the multiport fast memory system and can be used to construct a hypernode with 16—128 processors. In this paper we construct an interconnect Router, MRouter, on the basis of MCIM, which supports the pipelined Cut Through data transfer mode. The interconnection network made of MRouter has the lower latency and higher bandwidth. A concordant large scale parallel system can be implemented by connecting the MCIM hypernodes with MRouter network, because the same interconnect mechanism is applied in both the board level and machine level interconnection. In this paper we present the principle of MCIM (Memory Centric Interconnection Mechanism) and depict the structure of MRouter, a MCIM Router,and describes its data transferring procedure. In simulation experiment we test and compare the Memory Centric Interconnect with other communication techniques. At last we put forward a fast multiport memory model for current implementation.