A technology platform for monolithic wafer-level three-dimensional system-on-a-chip (3D-SoC) is presented, which uses wafer bonding with dielectric glues and Cu damascene inter-wafer interconnects. Four major processing steps, i.e., wafer alignment, wafer bonding, wafer thinning, and inter-wafer interconnection are delineated and characterized using a test vehicle of inter-wafer 3D via-chain structures. Continuous 3D via-chains are demonstrated for nominal via sizes of 2, 3, 4, and 8 μm. A viable baseline process flow that accounts for the capabilities and limitations of the various process steps is described. Possible extensions of this 3D-SoC technology platform are discussed for future low-cost hyper-integration of CMOS-based systems with very high performance, functionality and packaging density.