Novel low power pipelined FFT based on subexpression sharing for wireless LAN applications

This paper proposes a novel low power multiplierless radix-4 single-path delay commutator (R4SDC) FFT processor architecture for wireless LAN (IEEE 802.11 standard) applications, where short FFT are utilised in the implementation of the physical layer. The multiplierless architecture uses shift and addition operations to realize complex multiplications. By combining a new commutator architecture, and low power butterfly architectures with this approach, the resulting power savings are around 19% and 35% for 64-point and 16-point radix-4 FFT respectively, as compared to a conventional FFT architecture based on non-Booth coded Wallace tree multiplier.

[1]  Tughrul Arslan,et al.  A triple port RAM based low power commutator architecture for a pipelined FFT processor , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[2]  Naresh R. Shanbhag,et al.  Low-power FFT via reduced precision redundancy , 2001, 2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578).

[3]  Bevan M. Baas,et al.  A low-power, high-performance, 1024-point FFT processor , 1999, IEEE J. Solid State Circuits.

[4]  Chein-Wei Jen,et al.  Hardware-efficient DFT designs with cyclic convolution and subexpression sharing , 2000 .

[5]  Shousheng He,et al.  Design and implementation of a 1024-point pipeline FFT processor , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

[6]  Mohd. Hasan.  Low power techniques and architectures for multicarrier wireless receivers , 2003 .

[7]  Kai Hwang,et al.  Computer arithmetic: Principles, architecture, and design , 1979 .

[8]  E. V. Jones,et al.  A pipelined FFT processor for word-sequential data , 1989, IEEE Trans. Acoust. Speech Signal Process..

[9]  Hannu Tenhunen,et al.  A new VLSI-oriented FFT algorithm and implementation , 1998, Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372).

[10]  U. Jagdhold,et al.  A 64-point Fourier transform chip for high-speed wireless LAN application using OFDM , 2004, IEEE Journal of Solid-State Circuits.

[11]  John S. Thompson,et al.  A novel coefficient ordering based low power pipelined radix-4 FFT processor for wireless LAN applications , 2003, IEEE Trans. Consumer Electron..