Single-faced Boolean Functions and their Minimization

This paper identifies a new class of Boolean functions called single-faced functions. Single-faced functions are extensions of the related double-faced core functions which have fewer supporting variables. It is proven that single-faced functions can be simplified to their core functions with respect to Sum of Product minimization, general factored forms minimization and Ordered Binary Decision Diagram (OBDD) minimization. Even if a function f is not single-faced, it must contain single-faced function restrictions if f is not the odd‐even parity function. Experimental results show that single-faced functions are common in benchmark circuits. The structure of OBDDs of single-faced functions is studied in detail giving insights which can lead to efficient OBDD minimization algorithms. Moreover it is proven that for symmetric functions and the newly identified complete single-faced functions, any variable ordering will lead to identical OBDDs, which implies that traditional OBDD minimization algorithms will search exhaustively for those functions. Therefore for OBDD minimization, symmetry detection is mandatory in order to avoid unnecessary permutation of variables.

[1]  Alan Natapoff Irreducible Topological Components of an Arbitrary Boolean Truth Function and Generation of Their Minimal Coverings , 1967, JACM.

[2]  Christoph Meinel,et al.  Efficient Boolean Manipulation With OBDD's can be Extended to FBDD's , 1994, IEEE Trans. Computers.

[3]  Robert K. Brayton,et al.  Multilevel logic synthesis , 1990, Proc. IEEE.

[4]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[5]  Malgorzata Marek-Sadowska,et al.  Universal logic gate for FPGA design , 1994, ICCAD 1994.

[6]  Don E. Ross,et al.  Functional approaches to generating orderings for efficient symbolic representations , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[7]  Amar Mukhopadhyay Recent developments in switching theory , 1971 .

[8]  Constantin Halatsis,et al.  Irredundant Normal Forms and Minimal Dependence Sets of a Boolean Function , 1978, IEEE Transactions on Computers.

[9]  Don E. Ross,et al.  Heuristics to compute variable orderings for efficient manipulation of ordered binary decision diagrams , 1991, 28th ACM/IEEE Design Automation Conference.

[10]  Robert K. Brayton,et al.  SIS : A System for Sequential Circuit Synthesis Electronics Research Laboratory Memorandum , 1992 .

[11]  P. R. Stephan,et al.  SIS : A System for Sequential Circuit Synthesis , 1992 .

[12]  Malgorzata Marek-Sadowska,et al.  Universal logic gate for FPGA design , 1994, ICCAD '94.

[13]  R. Rudell Dynamic variable ordering for ordered binary decision diagrams , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[14]  Chen-Shang Lin,et al.  On the OBDD-Representation of General Boolean Functions , 1992, IEEE Trans. Computers.

[15]  Randal E. Bryant,et al.  On the Complexity of VLSI Implementations and Graph Representations of Boolean Functions with Application to Integer Multiplication , 1991, IEEE Trans. Computers.

[16]  Randal E. Bryant,et al.  Symbolic Boolean manipulation with ordered binary-decision diagrams , 1992, CSUR.

[17]  R. Bryant Graph-Based Algorithms for Boolean Function Manipulation12 , 1986 .

[18]  C. Leonard Berman,et al.  Circuit width, register allocation, and ordered binary decision diagrams , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  Data structures, minimization and complexity of boolean functions , 1996 .

[20]  Albert R. Wang,et al.  Logic verification using binary decision diagrams in a logic synthesis environment , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[21]  Kenneth J. Supowit,et al.  Finding the Optimal Variable Ordering for Binary Decision Diagrams , 1990, IEEE Trans. Computers.