A high-speed low-power calibrated flash ADC

A 2-GS/s 6-bit flash analog-to-digital converter (ADC) in 90nm CMOS is presented. Using the reference-voltage-interpolated calibration reduces bandwidth requirements on the comparator to enable high sampling rates with low power consumption. The ADC consumes 28 mW and occupies 0.35 mm2. The proposed calibrated technique improves ENOB from 3.0 to 5.1 with an input sinusoid at Nyquist frequency.

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