Through wafer via holes manufacturing by variable isotropy Deep RIE process for RF applications

This paper reports a method on the manufacturing of through silicon wafer via holes with tapered walls by Deep Reactive Ion Etching using the opportunity to change the isotropy in the DRIE equipments during processing. By using consecutively anisotropic and isotropic etching steps it is possible to enlarge the dimension of via holes on one side of the wafer, while on the other side dimension is set by the initial etching window. The optimized process was used to obtain via’s with a good control over the walls angles for two etching windows sizes (100 and 20 μm respectively) on 300 μm thick silicon wafers. After process optimization, a deviation smaller than 10% of the manufactured via holes across the wafers was observed for the designed walls angles of 11.3° and 21.8°. Barrier and seed layers were deposited in via’s performed by Physical Vapor Deposition techniques with a very good coverage of the walls. Finally, gold electroplating was used to fill the narrow part of via’s.

[1]  Preben Storås,et al.  Development of cost-effective high-density through-wafer interconnects for 3D microsystems , 2006 .

[2]  F. Marty,et al.  Advanced etching of silicon based on deep reactive ion etching for silicon high aspect ratio microstructures and three-dimensional micro- and nanostructures , 2005, Microelectron. J..

[3]  Y. Mita,et al.  A simultaneous vertical and horizontal self-patterning method for deep three-dimensional microstructures , 2007 .

[4]  M. Bartek,et al.  Comparison of via-fabrication techniques for through-wafer electrical interconnect applications , 2004, 2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546).

[5]  C. S. Premachandran,et al.  A novel electrically conductive wafer through hole filled vias interconnect for 3D MEMS packaging , 2003, 53rd Electronic Components and Technology Conference, 2003. Proceedings..

[6]  Alexander Polyakov,et al.  Mechanical Reliability of Silicon Wafers with Through-Wafer Vias for Wafer-Level Packaging , 2002, Microelectron. Reliab..

[7]  Weileun Fang,et al.  Implementation of three-dimensional SOI-MEMS wafer-level packaging using through-wafer interconnections , 2007 .

[8]  H. Reichl,et al.  High aspect ratio TSV copper filling with different seed layers , 2008, 2008 58th Electronic Components and Technology Conference.

[9]  Pasqualina M. Sarro,et al.  Continuous deep reactive ion etching of tapered via holes for three-dimensional integration , 2008 .

[10]  Ole Hansen,et al.  Investigations of the isotropic etch of an ICP source for silicon microlens mold fabrication , 2005 .

[11]  Mitsuhiro Shikida,et al.  The mechanism of selective corrugation removal by KOH anisotropic wet etching , 2010 .

[12]  Luis Fernando Velasquez-Garcia,et al.  Design and Fabrication of DRIE-Patterned Complex Needlelike Silicon Structures , 2010, Journal of Microelectromechanical Systems.