Design of prominent Time-to-Digital Converter using single electron transistor operating at room temperature

Single electron transistor (SET) has the potential for low power applications due to its low power consumption and high performance. In this paper, we have proposed a novel implementation of fully digital Time-to-Digital Converter (TDC) using single electron transistor and 16nm CMOS FINFET technology. A delay line based, 8-bit resolution TDC is implemented. The proposed SET based TDC has 49.7% power consumption improvement over 16nm CMOS technology. Performance of SET based TDC is also compared and found to be better than the CMOS based implementation. The design is implemented in CADENCE virtuoso design environment. Although the SET has low driving capabilities there are many alternatives ways to improve it at the cost of power and area. Since SET is power and area efficient, trade-offs would not be an issue for highly complex digital designs. SET is a futuristic device and has many aspects to explore in the future.

[1]  Akira Matsuzawa,et al.  An All-Digital Reconfigurable Time-Domain ADC for Low-Voltage Sensor Interface in 65nm CMOS Technology , 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[2]  Shakti Prasad Senapati.  Design of a simple digital ADC using only digital blocks and delay element circuit , 2016, 2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT).

[3]  Dominique Drouin,et al.  Towards nano-computing blocks using room temperature double-gate single electron transistors , 2014, 2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS).

[4]  D. Drouin,et al.  Simulation and Design Methodology for Hybrid SET-CMOS Integrated Logic at 22-nm Room-Temperature Operation , 2012, IEEE Transactions on Electron Devices.

[5]  Biswajit Mishra,et al.  Design of an all-digital, low power time-to-digital converter in 0.18μm CMOS , 2017, 2017 7th International Symposium on Embedded Computing and System Design (ISED).

[6]  S. Mahapatra,et al.  Analytical modeling of single electron transistor for hybrid CMOS-SET analog IC design , 2004, IEEE Transactions on Electron Devices.

[7]  Manoj Sachdev,et al.  A fully digital ADC using a new delay element with enhanced linearity , 2008, 2008 IEEE International Symposium on Circuits and Systems.