Order Free Consistency: Towards a Fully Asynchronous Memory Model

Computer architects are now studying a new generation of multi-core chip architectures that may integrate hundreds of processing cores and memory banks on a single chip employing a shared memory organization. A system may consist of many such chips (nodes) and an increasing demand to support high bandwidth and shared-address space between nodes. Furthermore, the inter-chip and intra-chip interconnections are also fast progressing with optical inter-chip and photonics intra-chip technology promising unprecedented bandwidth as well as multi-channel reordering capabilities. This paper focuses on the following fundamental question: can we have a memory model that is truly asynchronous that is: (1) memory operations can be issued freely from the processors without blocking by any memory based data dependence, and (2) the memory transmissions can travel through the interconnection network freely without worrying that they may arrive at the destination out of order. Furthermore, such a memory model must be realizable: that is, we can define an operational model 1 (hence construct an abstract machine) that can fully explore the above features during program execution. The terms “operational model” and “operational semantics” can be exchangeable in this paper.