Network flow-based simultaneous retiming and slack budgeting for low power design

Low power design has become one of the most significant requirements when CMOS technology entered the nanometer era. Therefore, timing budget is often performed to slow down as many components as possible so that timing slacks can be applied to reduce the power consumption while maintaining the performance of the whole design. Retiming is a procedure that involves the relocation of flip-flops (FFs) across logic gates to achieve faster clocking speed. In this paper we show that the retiming and slack budgeting problem can be formulated to a convex cost dual network flow problem. Both the theoretical analysis and experimental results show the efficiency of our approach which can not only reduce power consumption by 8.9%, but also speedup previous work by 500 times.

[1]  Yu Wang,et al.  Simultaneous slack budgeting and retiming for synchronous circuits optimization , 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

[2]  Majid Sarrafzadeh,et al.  Predicting potential performance for digital circuits , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Majid Sarrafzadeh,et al.  A unified theory of timing budget management , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[4]  Dorit S. Hochbaum,et al.  Solving the Convex Cost Integer Dual Network Flow Problem , 1999, Manag. Sci..

[5]  David Blaauw,et al.  Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment , 2004, Proceedings. 41st Design Automation Conference, 2004..

[6]  Hai Zhou,et al.  Design Closure Driven Delay Relaxation Based on Convex Cost Network Flow , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[7]  Dennis Sylvester,et al.  A new algorithm for improved VDD assignment in low power dual VDD systems , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[8]  Hai Zhou,et al.  A new efficient retiming algorithm derived by formal manipulation , 2008, TODE.

[9]  David G. Chinnery,et al.  Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization , 2003, ISLPED '03.

[10]  Charles E. Leiserson,et al.  Retiming synchronous circuitry , 1988, Algorithmica.

[11]  Sachin S. Sapatnekar,et al.  Efficient retiming of large circuits , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[12]  Hai Zhou,et al.  Clock Skew Scheduling with Delay Padding for Prescribed Skew Domains , 2007, 2007 Asia and South Pacific Design Automation Conference.

[13]  Hai Zhou,et al.  An efficient retiming algorithm under setup and hold constraints , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[14]  Ravi Nair,et al.  Generation of performance constraints for layout , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Satoshi Goto,et al.  Voltage-island driven floorplanning considering level-shifter positions , 2009, GLSVLSI '09.

[16]  Yu Hu,et al.  Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[17]  Hai Zhou,et al.  Efficient algorithms for buffer insertion in general circuits based on network flow , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[18]  Evangeline F. Y. Young,et al.  Network flow-based power optimization under timing constraints in MSV-driven floorplanning , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[19]  De-Sheng Chen,et al.  An exact algorithm for low power library-specific gate re-sizing , 1996, DAC '96.

[20]  Xianlong Hong,et al.  IPOSA: A Novel Slack Distribution Algorithm for Interconnect Power Optimization , 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

[21]  Hai Zhou.  Deriving a new efficient algorithm for min-period retiming , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[22]  Ravindra K. Ahuja,et al.  Network Flows: Theory, Algorithms, and Applications , 1993 .

[23]  Hai Zhou,et al.  An efficient incremental algorithm for min-area retiming , 2008, 2008 45th ACM/IEEE Design Automation Conference.