CMOS logic gate performance variability related to transistor network arrangements

The rapid scaling of CMOS technology has resulted in drastic variations of process parameters. Since different transistor arrangements present different electrical characteristics, this work analyzes the impact of process variability in performance of logic gates, according to their topology and the relative position of the switching device in the network. Results have been obtained through Monte-Carlo simulations and design guidelines for parametric yield improvement have been derived.

[1]  Shekhar Y. Borkar,et al.  Designing reliable systems from unreliable components: the challenges of transistor variability and degradation , 2005, IEEE Micro.

[2]  Rajendran Panda,et al.  Slope propagation in static timing analysis , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[3]  Yu Cao,et al.  Predictive Technology Model for Nano-CMOS Design Exploration , 2006, 2006 1st International Conference on Nano-Networks and Workshops.

[4]  Hidetoshi Onodera,et al.  A Statistical Gate-Delay Model Considering Intra-Gate Variability , 2003, ICCAD.

[5]  Gene A. Frantz,et al.  The Texas Instruments TMS320C25 Digital Signal Microcomputer , 1986, IEEE Micro.

[6]  Alessandro Trifiletti,et al.  A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  Dennis Sylvester,et al.  Parametric Yield Analysis and Optimization in Leakage Dominated Technologies , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Kaushik Roy,et al.  Novel sizing algorithm for yield improvement under process variation in nanometer technology , 2004, Proceedings. 41st Design Automation Conference, 2004..

[9]  Kaushik Roy,et al.  Estimation of delay variations due to random-dopant fluctuations in nanoscale CMOS circuits , 2005, IEEE Journal of Solid-State Circuits.

[10]  José Pineda de Gyvez,et al.  Threshold voltage and power-supply tolerance of CMOS logic design families , 2000, Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[11]  Sani R. Nassif,et al.  Design for Manufacturability and Statistical Design - A Constructive Approach , 2007, Series on integrated circuits and systems.

[12]  Chenming Hu,et al.  Characterization of spatial intrafield gate CD variability, its impact on circuit performance, and spatial mask-level correction , 2004, IEEE Transactions on Semiconductor Manufacturing.

[13]  Rosa Junior,et al.  Automatic generation and evaluation of transistor networks in different logic styles , 2008 .