Performance Analysis of Mesh Interconnection Networks with Deterministic Routing

This paper develops detailed analytical performance models for k-ary n-cube networks with single-hit or infinite buffers, wormhole routing, and the nonadaptive deadlock-free routing scheme proposed by Dally and Seitz (1987). In contrast to previous performance studies of such networks, the system is modeled as a closed queueing network that: includes the effects of blocking and pipelining of messages in the network; allows for arbitrary source-destination probability distributions; and explicitly models the virtual channels used in the deadlock-free routing algorithm. The models are used to examine several performance issues for 2-D networks with shared-memory traffic. These results should prove useful for engineering high-performance systems based on low-dimensional k-ary n-cube networks. >

[1]  Anant Agarwal,et al.  Limits on Interconnection Network Performance , 1991, IEEE Trans. Parallel Distributed Syst..

[2]  Leonard Kleinrock,et al.  Performance analysis of finite-buffered multistage interconnection networks with a general traffic pattern , 1991, SIGMETRICS '91.

[3]  Gyungho Lee,et al.  The Effectiveness of Combining in Shared Memory Parallel Computer in the Presence of "Hot Spots" , 1986, ICPP.

[4]  K. Mani Chandy,et al.  Linearizer: a heuristic algorithm for queueing network models of computing systems , 1982, CACM.

[5]  A. Gupta,et al.  Exploring the benefits of multiple hardware contexts in a multiprocessor architecture: preliminary results , 1989, ISCA '89.

[6]  Kevin Bolding Non-Uniformities Introduced by Virtual Channel Deadlock Prevention , 1992 .

[7]  William J. Dally,et al.  Performance Analysis of k-Ary n-Cube Interconnection Networks , 1987, IEEE Trans. Computers.

[8]  Richard J. Enbody,et al.  Performance Degradation in Large Wormhole-Routed Interprocessor Communication Networks , 1990, International Conference on Parallel Processing.

[9]  Derek L. Eager,et al.  An analytic model of multistage interconnection networks , 1990, SIGMETRICS '90.

[10]  Laxmi N. Bhuyan,et al.  High-performance computer architecture , 1995, Future Gener. Comput. Syst..

[11]  William J. Dally,et al.  Deadlock-Free Message Routing in Multiprocessor Interconnection Networks , 1987, IEEE Transactions on Computers.

[12]  Anant Agarwal,et al.  APRIL: a processor architecture for multiprocessing , 1990, ISCA '90.

[13]  William J. Dally,et al.  A VLSI Architecture for Concurrent Data Structures , 1987 .

[14]  Michael D. Noakes,et al.  The J-machine multicomputer: an architectural evaluation , 1993, ISCA '93.

[15]  Gregory F. Pfister,et al.  “Hot spot” contention and combining in multistage interconnection networks , 1985, IEEE Transactions on Computers.

[16]  Erol Gelenbe Performance analysis of the connection machine , 1990, SIGMETRICS '90.

[17]  Shekhar Y. Borkar,et al.  iWarp: an integrated solution to high-speed parallel computing , 1988, Proceedings. SUPERCOMPUTING '88.

[18]  Mary K. Vernon,et al.  An accurate and efficient performance analysis technique for multiprocessor snooping cache-consistency protocols , 1988, ISCA '88.

[19]  Leonard Kleinrock,et al.  Virtual Cut-Through: A New Computer Communication Switching Technique , 1979, Comput. Networks.

[20]  Nian-Feng Tzeng,et al.  Distributing Hot-Spot Addressing in Large-Scale Multiprocessors , 1987, IEEE Transactions on Computers.

[21]  J DallyWilliam,et al.  Performance Analysis of k-ary n-cube Interconnection Networks , 1990 .

[22]  Anoop Gupta,et al.  The Stanford Dash multiprocessor , 1992, Computer.