SIGMA: a VLSI systolic array implementation of a Galois field GF(2 m) based multiplication and division algorithm

Finite or Galois fields are used in numerous applications like error correcting codes, digital signal processing and cryptography. The design of efficient methods for Galois field arithmetic such as multiplication and division is critical for these applications. A new algorithm based on a pattern matching technique for computing multiplication and division in GF(2/sup m/) is presented. An efficient systolic architecture is described for implementing the algorithm which can produce a new result every clock cycle and the multiplication and division operations can be interleaved. The architecture has been implemented using 2- mu m CMOS technology. The chip yields a computational rate of 33.3 million multiplications/divisions per second. >

[1]  P ? ? ? ? ? ? ? % ? ? ? ? , 1991 .

[2]  Kurt Mehlhorn,et al.  AT²-Optimal Galois Field Multiplier for VLSI , 1989, IEEE Trans. Computers.

[3]  Bing Bing Zhou.  A New Bit-Serial Systolic Multiplier Over GF(2m) , 1988, IEEE Trans. Computers.

[4]  Eiji Fujiwara,et al.  Error-control coding for computer systems , 1989 .

[5]  Thomas C. Bartee,et al.  Computation with Finite Fields , 1963, Inf. Control..

[6]  Trieu-Kien Truong,et al.  Systolic Multipliers for Finite Fields GF(2m) , 1984, IEEE Transactions on Computers.

[7]  Gui Liang Feng.  A VLSI Architecture for Fast Inversion in GF(2^m) , 1989, IEEE Trans. Computers.

[8]  Trieu-Kien Truong,et al.  VLSI Architectures for Computing Multiplications and Inverses in GF(2m) , 1983, IEEE Transactions on Computers.

[9]  Charles M. Rader,et al.  Number theory in digital signal processing , 1979 .

[10]  Antonio Pincin.  A New Algorithm for Multiplication in Finite Fields , 1989, IEEE Trans. Computers.

[11]  Stafford E. Tavares,et al.  A Fast VLSI Multiplier for GF(2m) , 1986, IEEE J. Sel. Areas Commun..

[12]  J. Kowalchuk,et al.  Packets to the editor , 1979 .

[13]  Dingyi Pei,et al.  A VLSI DEsign for Computing Exponentiations in GF(2^m) and Its Application to Generate Pseudorandom Number Sequences , 1990, IEEE Trans. Computers.

[14]  Craig K. Rushforth,et al.  A Cellular-Array Multiplier for GF(2m) , 1971, IEEE Transactions on Computers.

[15]  Shu Lin,et al.  An introduction to error-correcting codes , 1970 .

[16]  Hideki Imai,et al.  A Construction Method of High-Speed Decoders Using ROM's for Bose–Chaudhuri–Hocquenghem and Reed–Solomon Codes , 1987, IEEE Transactions on Computers.

[17]  Kai Hwang,et al.  Computer architecture and parallel processing , 1984, McGraw-Hill Series in computer organization and architecture.