Schottky-Barrier Height Tuning by Means of Ion Implantation Into Preformed Silicide Films Followed by Drive-In Anneal

An experimental study on Schottky-barrier height (SBH) tuning using ion implantation followed by drive-in anneal of As, B, In, and P in preformed NiSi and PtSi films is presented. Measured on B-implanted NiSi and PtSi Schottky diodes, the effective SBH on n-type Si is altered to ~1.0 eV. For As- and P-implanted diodes, the SBH on p-type Si can be tuned to around 0.9 eV. The process window for the most pronounced SBH modification is dopant dependent.

[1]  C. R. Helms,et al.  Experimental investigation of a PtSi source and drain field emission transistor , 1995 .

[2]  Pt-silicide source and drain SOI-MOSFET operating in bi-channel modes , 1998, 56th Annual Device Research Conference Digest (Cat. No.98TH8373).

[3]  C. Hu,et al.  Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regime , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[4]  M. Tao,et al.  Removal of dangling bonds and surface states on silicon (001) with a monolayer of selenium , 2003 .

[5]  J. Koga,et al.  Solution for high-performance Schottky-source/drain MOSFETs: Schottky barrier height engineering with dopant segregation technique , 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

[6]  M. Fritze,et al.  High-speed Schottky-barrier pMOSFET with f/sub T/=280 GHz , 2004, IEEE Electron Device Letters.

[7]  Jae-Heon Shin,et al.  A 50-nm-gate-length erbium-silicided n-type Schottky barrier metal-oxide-semiconductor field-effect transistor , 2004 .

[8]  C. Faulkner,et al.  A new route to zero-barrier metal source/drain MOSFETs , 2004, IEEE Transactions on Nanotechnology.

[10]  Tsu-Jae King,et al.  A comparison study of symmetric ultrathin-body double-gate devices with metal source/drain and doped source/drain , 2005, IEEE Transactions on Electron Devices.

[11]  Qing-Tai Zhao,et al.  Tuning of NiSi/Si Schottky barrier heights by sulfur segregation during Ni silicidation , 2005 .

[12]  Y. Tsunashima,et al.  High-Performance FinFET with Dopant-Segregated Schottky Source/Drain , 2006, 2006 International Electron Devices Meeting.

[13]  J. Koga,et al.  1 nm NiSi/Si Junction Design based on First-Principles Calculation for Ultimately Low Contact Resistance , 2006, 2006 International Electron Devices Meeting.

[14]  Robust, scalable self-aligned platinum silicide process , 2006 .

[15]  J. Koga,et al.  Ultra Low Voltage Operations in Bulk CMOS Logic Circuits with Dopant Segregated Schottky Source/Drain Transistors , 2006, 2006 International Electron Devices Meeting.

[16]  J. Larson,et al.  Overview and status of metal S/D Schottky-barrier MOSFET technology , 2006, IEEE Transactions on Electron Devices.

[17]  R.A. Vega.  On the modeling and design of Schottky field-effect transistors , 2006, IEEE Transactions on Electron Devices.