Multiple pass exposure in e-beam lithography: application to the sub-22nm nodes

Electron Beam Direct Write lithography is used in the IC manufacturing industry to sustain optical lithography for prototyping applications and low volume manufacturing. It is also used in R&D to develop the technological nodes ahead of mass production. As microelectronics is now moving towards the 32nm node and beyond, the need to accurately control the dimensions and the roughness of the features becomes tighter. As a consequence the requirements in terms of process window and resolution for the electron beam tools are more stringent. However the standard proximity effects corrections show difficulties to provide the required energy latitude for the sub-22nm nodes. A new approach is thus required to improve the patterning capabilities of electron beam lithography. In previous papers a new writing strategy based on multiple pass exposure has been introduced and optimized to pattern critical dense lines. This technique consists in adding small electron Resolution Improvement Features (eRIF) on top of the nominal structures. Previous studies have demonstrated that the energy latitude and the writing time can be optimized by tuning the design of the eRIF. A methodology to implement the eRIF on dense lines has also been established. The goal of this paper is to extend the use of the multiple pass exposure strategy to more complex designs taken from products layouts. The most critical layers of SRAM and Logic layouts down to the 16nm node are corrected with this advanced correction technique. The results from wafer exposures show that the edge roughness of the features is decreased and the energy latitude of our process is multiplied by two for each SRAM layer. Thanks to these improvements of the patterning capabilities of our electron beam tool, a gain in resolution of one technological node is achieved. Finally a method is proposed to implement the multiple pass exposure within an automated data preparation flow.