Assessment of the spinning-current efficiency in cancelling the 1/f noise of Vertical Hall Devices through accurate FEM modeling

The Vertical Hall Device integrable in a shallow N-well, and thus compatible with Low-Voltage CMOS processes, i.e. the LV-VHD, was proposed five years ago. Its layout is similar to the layout of the HV-VHD, i.e. the conventional 5-contact VHD integrated in the deep N-well of High-Voltage processes. However, in the LV-VHD, the Hall voltage is picked-up from the external contacts while it is picked-up from the internal contacts in the HV-VHD. Such sensing schemes make not obvious the application of the well-known Spinning-Current Technique (SCT) used in Horizontal Hall Device (HHD) for offset and 1/f noise attenuation. In this paper, an accurate Finite Element Modeling (FEM) analysis of the SCT for VH-Devices is presented. All the second-order effects which influence the VHD, i.e. the Junction Field Effect (JFE) and the Carrier Velocity Saturation (CVS), are taken into account. Simulation results carried out on a LV-VHD show that SCT remains efficient even under high current biasing, i.e. when CVS takes place.